The integrated circuits scale down along with the advanced technology nodes. The scaling of integrated circuit faces various challenges that include patterning and other fabrication process. For example, shallow trench isolation (STI) features are formed in a silicon substrate to define various active regions for various devices, such as field effect transistors (FETs). However, the formation of the STI features by the existing methods has various concerns. In one example, the step height cannot be properly controlled to achieve expected device performance. In another example, the step height cannot be consistently controlled from wafer to wafer. In another example, various particles are introduced to the semiconductor substrate during the formation of the STI features.
Accordingly, there is a need for a method and a system to address these concerns.